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microcontroller sunplus technology co. reserves the right to change this documentation without prior notice. information provided by sunplus t echnology co. is believed to be accurate and reliable. however, sunplus technology co. makes no warranty for any errors which may appear in this document. contact sunplus technology co. to obtain the latest version of device specifications before placing your order. no responsibility is assumed by sunplus technology co. for any infringement of patent or other rights of third parties which may result from its use . in addition, sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems , where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written appr oval of sunplus. page 1 SPMC02A general description sunplus SPMC02A contains a sunplus 8 bit micro-controller units (mcu), 4.5k bytes rom, 128 bytes sram and 2 8-bit timers. the advanced sub-micron cmos process technology ensures SPMC02A?s high performance, high reliability and advanced functions. in addition, SPMC02A also provides high sink current with slow output transition port pins, multi external interrupt pins, low voltage reset (lvr) function, and multi oscillator options. SPMC02A offers one of the best cost/performance ratios in the industry. block diagram osc. ckt 4.5k bytes rom $600~$fff & $1800~$1fff 128 bytes ram $80 ~ $ff 8 - bit cpu reset(pb4) irq(pb5) xo/r xi i/o port & external reset pin i/o port & external irq pin i/o port & external interrupt i/o port & 2 set comparator circuit i/o port i/o port & pwm waveform output i/o port & external clock pin timer 1 & rti & watch_dog timer timer 2 & 6 bits pwm waveform generator interrupt generator & reset generator pd3-0 pb3-1 pa6 pa7 pa3-0 pc7-0 pa4,pa5 pb0 pb7 pb6 /13 /1 /1 /8 /3 vdd vss /1 /1 address bus data bus features built-in 8-bit sunplus cpu core and up to 6.0mhz clock operation 128 bytes sram 4.5k bytes rom for users' program on-chip rc oscillator (only one external resistor needed) or crystal input or external clock input up to 14 external interrupt pins. 1 i/o can be with reset input selected by mask option. 4 i/os with slow output transition function 1 8-bits read-only timer with real time interrupt 1 8-bits re-loadable timer with programmable 8 stage pre-scalar. 1 external clock input pin for timer 2 1 6-bit pwm waveform generator 1 watchdog timer built-in two comparators power-saving stop & wait modes illegal address reset low voltage reset circuit operation voltage range: 2.4v - 5.5v provides chip form, package in pdip or soic. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 2 nov. 07, 2000 version: 1.5 cpu the 8-bit micro-controller of SPMC02A is a sunplus proprietary high performance processor equipped with accumulator, program counter, x register, stack pointer and processor status register. (the same as 6502 instruction?s structure.) SPMC02A is a fully static cmos design. the oscillation frequency could be varied from 200khz up to 6mhz depends on the requirements of applications. the SPMC02A development system includes a sunplus ice, evaluation chip and engineering development board. 1. processor status register bit 7 6 5 4 3 2 1 0 flag n v - b - i z c n: negative, v: overflow, b: brk command, i: irq disable, z: zero, c: carry 2. block diagram of sunplus cpu abl instruction register processor status register p instruction decode pch pcl input data latch idli data bus buffer index register x interrupt logic timing control clock generator accumulator a alu stack point register s abh register section reset irq nmi control section a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 address bus legend = 8bit line = 1 bit line d0 d1 d2 d3 d4 d5 d6 d7 clk 0 in r/w data bus rdy pd memory 1. memory map $0000 $0013 i/o registers $0014 $007f not used $0080 $00ff user sram 128 bytes $0400 $05ff $0600 $0fff program rom 2.5k bytes $1000 $17ff $1800 $1fff reserved for test 0.5k bytes rom not used program rom 2k bytes 2. ram total of 128 bytes of ram (including the stack) is available from $0080 through $00ff. the stack begins at address $00ff and proceeds down to $0080. 3. rom total of 5120 bytes of on-chip rom including 4608 (4.5k) bytes of user rom with 512 bytes of internal test rom from $400 to $5ff. user?s program can only be allocated from $0600 to $0fff and $1800 to $1fff. 4. nmi, reset, irq vectors the address of nmi (not provided in this chip), reset and irq are located from $1ffa to $1fff. that should be specified in the program as following: org $1ffa ;define SPMC02A chip ;interrupt vector. dw nmi_routine dw reset dw int_routine free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 3 nov. 07, 2000 version: 1.5 if customer uses sunplus ice and evaluation board, the address $7ffa when using evaluation board with eprom (for 27c256), the address of $7ffa must be defined as follows: org $7ffa ;interrupt vector for ;eprom with dw nmi_routine ;evaluation board. dw reset dw int_routine org $fffa ;interrupt vector for ;sunplus ice. dw nmi_routine dw reset dw int_routine oscillator the SPMC02A supports at-cut parallel resonant oscillated crystal /resonator or rc oscillator or external clock sources by mask option (select one from those three types). the design of application circuit should follow the vendors? specifications or recommendations. the diagrams listed below are typical x?tal/rosc circuits for most applications: clock source connection SPMC02A xi xo/r SPMC02A xi xo/r SPMC02A xi xo/r 20 pf 20 pf rosc vdd unconnected external clock (a) crystal or ceramic resonator connections (b) rc oscillator connections (c) external mask options the SPMC02A has the following mask options: 1). oscillator select: crystal / resonator or external resistor or external clock input. 2). pa5 - 0, pb0, pb3, pb6, pb7 & pc7 - 0 pull-up/down: pull-down or pull-up. 3). pa3 - 0 external interrupt capability: enable or disable. 4). external interrupt trigger (pa3 - 0 and irq): edge trigger or edge-level trigger. 5). reset / pb4 pin: pb4 i/o or i/o with reset input function. 6). timer 1 clock: f cpu /4 or f cpu /1. 7). watch - dog timer reset: enable or disable. 8). low voltage reset: reset on vcc while lower than 2.2v voltage or no detection. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 4 nov. 07, 2000 version: 1.5 function control register all function register will be set to ?0? when a reset is occurred except the rt1 and rt0 will be set to ?1? when a reset is occ urred. addr register r/w 7 6 5 4 3 2 1 0 enable $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pa w (0) (0) (0) (0) (0) (0) (0) (0) $0001 port b data r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pb w (0) (0) (0) (0) (0) (0) (0) (0) $0002 r (0) (0) (0) (0) (0) (0) (0) (0) 0 = in dpa port a data direction w dpa7 dpa6 dpa5 dpa4 dpa3 dpa2 dpa1 dpa0 1 = out $0003 r (0) (0) (0) (0) (0) (0) (0) (0) 0 = in dpb port b data direction w dpb7 dpb6 dpb5 dpb4 dpb3 dpb2 dpb1 dpb0 1 = out $0004 r tof(0) rtif(0) tofe rtie 0(0) 0(0) rt1 rt0 tcs1 timer control & status w (0) (0) tofr rtifr (1) (1) 1 = set $0005 r tmr7(0) tmr6(0) tmr5(0) tmr4(0) tmr3(0) tmr2(0) tmr1(0) tmr0(0) tcr1 timer counter register w $0006 r (0) (0) irqf2 irqe2 irqf irqf1 irqe1 irqe irqs irq control & status w irqr1 irqr (0) (0) (0) (0) (0) (0) 1 = set $0007 r cpd1(0) cpd0(0) cpif(0) (0) (0) (0) 1 = clr cpwd watch dog timer status w cprs1 cprs0 cpie cpiph cpe wdt /set $0008 stop & wait r snw w stop(0) wait(0) 1 = set $0009 r (0) (0) (0) (0) (0) (0) (0) rpa porta pullup / down register. wsle rpa5 rpa4 rpa3 rpa2 rpa1 rpa0 0 = en $000a r (0) (0) (0) (0) (0) (0) (0) rpb portb pullup / down register. wrpb7 rpb6 rpb4 rpb3 rpb2 rpb1 rpb0 0 = en $000b r (0) (0) (0) (0) (0) (0) (0) (0) rpc port c pull-up/ down register. w rpc7 rpc6 rpc5 rpc4 rpc3 rpc2 rpc1 rpc0 0 = en $000c r c7 c6 c5 c4 c3 c2 c1 c0 pc port c data w (0) (0) (0) (0) (0) (0) (0) (0) $000d r (0) (0) (0) (0) (0) (0) (0) (0) 0 = in dpc port c data direction w dpc7 dpc6 dpc5 dpc4 dpc3 dpc2 dpc1 dpc0 1 = out $000e r ps2 ps1 ps0 cks (0) (0) tof2 (0) tcs2 timer control & status 2 w (0) (0) (0) (0) tm2e tofr2 (0) tofe2 1 = set $000f r tm2r7 tm2r6 tm2r5 tm2r4 tm2r3 tm2r2 tm2r1 tm2r0 tcr2 timer counter register 2 w (0) (0) (0) (0) (0) (0) (0) (0) $0010 pwm waveform r (0) (0) pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 pwmc control w pwms pwme (0) (0) (0) (0) (0) (0) 1 = set $0011 port d data r (0) (0) (0) (0) 0 = in dpd direction w dpd3 dpd2 dpd1 dpd0 1 = out $0012 r d3 d2 d1 d0 pd port d data w (0) (0) (0) (0) $0013 r (0) (0) (0) (0) rpd port d pull-up register w rpd3 rpd2 rpd1 rpd0 the value of bracket () is power-on default value. the gray block is reserved. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 5 nov. 07, 2000 version: 1.5 i/o and control register - see appendix a, ~ g (i/o diagram) total of 28 i/os (grouped into four ports pa, pb, pc, and pd) are provided. the descriptions are as follows: 1). the 8 i/os are normal i/o ports: pa6, port b (pb3 - 0) and port d (pd3 - 0). 2). there are 13 i/os used for i/o or i/o with external interrupt. the pa3 - 0 can be mask-option for i/o or i/o with external interrupt. the pa7 & pc7 - 0 can be programmed as i/o or i/o with external interrupt. 3). there are 3 i/os used to comparator function. the pa4 and pa5 are comparator input pins. the pb0 is reference voltage input pin for comparator. 4). the pb4 can be mask option to i/o or i/o with reset pin. 5). the pb5 can be programmed as i/o or i/o with irq pin. 6). the pb6 can be programmed as i/o or i/o with external clock input pin. 7). the pb7 can be programmed as i/o or i/o with pwm waveform output pin. 1. port a (pa7 - 0): (see appendix a, b, c) addr register 7 6 5 4 3 2 1 0 $0000 port a data data data data data data data data data 0 in in in in in in in in $0002 direction 1 out out out out out out out out 0 enable enable enable enable enable enable $0009 pull-up/down 1 always* pull-up always pull-up disable disable disable disable disable disable up/down resistor 5k ? 5k ? 100k ? 100k ? 100k ? 100k ? 100k ? 100k ? source/sink current -/8ma -/8ma -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma special function ext. int - comparator comparator ext. int ext. int ext. int ext. int note: this bit is defined as sle bit. please refer to slow transition enable for more detail. 2. port a data register ($0000 pa) porta?s output data will be determined by $0000 pa data register when porta is programmed as output. any read of porta data register will return the logical state of the i/o pin when porta is programmed as input. the pa data register is set to ?0? when a reset is occurred. 3. port a data direction register ($0002 dpa) the porta can be programmed as input or output by $0002 dpa register. when dpa = ?1?, the corresponding pin(s) is (are) programmed as output. when dpa = ?0?, the corresponding pin(s) is (are) programmed as input. the dpa is set to ?0? (input) when a reset is occurred. 4. port a pull-up/down control register ($0009 rpa) pa5 - 0 pull-up/down resistors can be mask option to pull-up or pull-down, but pa6, pa7 are always pull-up. the register, rpa, is used to enable or disable the pull-up/down resistors on pa5 - 0. when rpa = ?0? , it will enable pull-up/down resistor of corresponding pins (pa5 - 0) at input mode. when rpa = ?1? , it will disable the corresponding pull-up/down resistors at input mode only. no pull-up/down resistor is available at output mode. the rpa will be set to ?0? (enabling mode) by reset. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 6 nov. 07, 2000 version: 1.5 5. port b (pb7 - 0): (see appendix a, b, d, e, and f) addr register 7 6 5 4 3 2 1 0 $0001 port b data data data data data data data data data 0 in in in in in in in in $0003 direction 1 out out out out out out out out 0 enable enable - pull-up enable pull-up pull-up enable $000a pull-up/down 1 disable disable - disable disable disable disable disable up/down resistor 100k ? 100k ? - 100k ? 100k ? 100k ? 100k ? 100k ? source/sink current -8/8ma -8/8ma -/8ma -8/8ma -8/8ma -/25ma -/25ma -8/8ma special function pwm(o) ext. clock irq reset - - - vref* note*: vref is reference voltage for comparator. 6. port b data register ($0001 pb) port b?s output data are determined by $0001 pb data register when portb is programmed as output. any read of the port b data register will return the logic state of the i/o pin when portb is programmed as input. notice that data register is set to 0 when reset is occurred. 7. port b data direction register ($0003 dpb) the port b can be programmed as inputs or outputs by $0003 dpb register. when dpb = ?1?, the corresponding pin(s) is (are) programmed as output. when dpb = ?0?, the corresponding pin(s) is (are) programmed as input. the dpb is set to ?0? (input mode) when a reset is occurred. 8. port b pull-up/down control register ($000a rpb) pb0, pb3, pb6, pb7 pull-up/down resistor can be controlled by user?s program through mask option. pb1, pb2, pb4 have pull-up resistor through program control. pb5 does not have pull-up or pull-down resistor; it is an open-drain output only. the register, rpb, is used to enable or disable the pull-up/down resistors. when rpb = ?0? , it will enable pull-up/down resistor of corresponding pins (pb0, pb3, pb6, pb7) and enable pull-up resistor of corresponding pins (pb1, pb2, pb4) at input mode. when rpb = ?1? , it will disable the corresponding pull-up/down resistors at input mode only. no pulled up/down resistor is available during output mode. the rpb will be set to ?0? (enabling mode) by reset. 9. reset / pb4: (see appendix e) the reset/pb4 pin can be selected as i/o or i/o with reset function by mask option. the reset pin is the only external source of a reset when reset function is selected. this pin is connected to a schmitt trigger input gate, pull-up 100k ? by rpb (set $000a b4 = 0) & low active. pb4 pin is a normal i/o function when i/o function is selected. 10. irq / pb5: (see appendix f) the irq/pb5 pin can be selected as i/o or i/o with irq function by program. 1). when irq function is selected, the irq pin is the main external source of an interrupt with active-low polarity. this pin is connected to a schmitt trigger input. it is an open-drain mode and therefore it needs to be pulled-up externally. 2). when i/o function is selected, the pb5 pin is normal i/o function and open-drain always. thus, it needs add a resistor externally. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 7 nov. 07, 2000 version: 1.5 11. port c (pc7 - 0): (see appendix a) addr register 7 6 5 4 3 2 1 0 $000c port c data data data data data data data data data 0 in in in in in in in in $000d direction 1 out out out out out out out out 0 enable enable enable enable enable enable enable enable $000b pull-up/down 1 disable disable disable disable disable disable disable disable up/down resistor 100k ? 100k ? 100k ? 100k ? 100k ? 100k ? 100k ? 100k ? source/sink current -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma -8/8ma special function ext. int ext. int ext. int ext. int ext. int ext. int ext. int ext. int 12. port c data register ($000c pc) when port c is programmed as output, portc?s data is determined by $000c (pc data register). any read of the port c data register will return the logic state of the i/o pin when portc is programmed as input. the pc data register is set to ?0? when a reset is occurred. 13. port c data direction register ($000d dpc) port c can be programmed as input or output by $000d dpc register. when dpc = ?1?, the corresponding pin(s) is (are) programmed as output. the corresponding pin(s) is (are) programmed as input when dpc = ?0?. the dpc is set to ?0? (input mode) when a reset is occurred. 14. port c pull-up/down control register ($000b rpc) pc7 - 0 pull-up/down resistors can be mask option to pull-up or pull-down. the register, rpc, is used to enable or disable the pull-up/down resistors on pc7-0. when rpc = ?0?, it will enable pull-up/down resistor of corresponding pins (pc7 - 0) at input mode. when rpc = ?1?, it will disable pull-up/down resistor of corresponding pins (pc7 - 0) at input mode only. no pulled up/down resistor is available during output mode. the rpc will be set to ?0? (enabling mode) by reset. 15. port d (pd3 - 0): (see appendix g) addr register 7 6 5 4 3 2 1 0 $0012 port d data data data data data 0 in in in in $0011 direction 1 out out out out 0 pull-up pull-up pull-up pull-up $0013 pull-up/down 1 disable disable disable disable up/down resistor 100k ? 100k ? 100k ? 100k ? source/sink current -8/8ma -8/8ma -8/8ma -8/8ma 16. port d data register ($0012 pd) portd?s output data is determined by $0012 (pd data register) when portd is programmed as output. any read of the port d data register will return the logic state of the i/o pin when portd is programmed as input. the pd data register is set to ?0? when a reset is occurred. 17. port d data direction register ($0011 dpd) port d can be programmed as input or output by $0011 dpd register. the corresponding pin(s) is (are) programmed as output when dpd = ?1?. the corresponding pin(s) is (are) programmed as input when dpd = ?0?. the dpd is set to ?0? (input mode) when a reset is occurred. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 8 nov. 07, 2000 version: 1.5 18. port d pull-up control register ($0013 rpd) pd3 - 0 pull-up resistors can be programmed as enabled (0) or disabled (1) by $0013 rpd register. when rpd = ?0? , it will enable pull-up resistor of corresponding pin (pd3 - 0) at input mode. when rpd = ?1? , it will disable the corresponding pull-up resistor at input mode. no pull-up resistor is available during output mode. the rpd will be set to ?0? (enable mode) by reset. 19. high sink current port: (see appendix d) both of pb1 & pb2?s output current is able to sink 25ma. if connecting pb1 and pb2 together, 50ma of sink current will be generated. output sink current setting methods are as follows (dpb2 = dpb1 = 1): 1). the single sink current is 25ma when pb1 = 0 & pb2 = 1, or pb1 = 1 & pb2 = 0. 2). the pb1, pb2 single sink current is 25ma when pb1 = pb2 = 0. 3). the 50ma sink current can be created when pb1 and pb2 are set to ?0? and both are short together. example: pb0, pb7 - 3 set as input. pb1, pb2 as output. lda #%00000110 ;0 as input, 1 as ;output. sta dpb ;dpb equ $0003. lda #%11111001 ; sta rpb ; lda #%00000100 sta pb ;pb2 out ?low? & sink current as 25ma. lda #%00000010 sta pb ;pb1 out ?low? & sink current as 25ma. lda #%00000000 sta pb ;pb1, pb2 out ?low? & ;sink 25ma when ;single output or ;sink 50ma when pb1, ;pb2 short and ;together output. 20. external interrupt input ports: (see appendix a, c, i) the pa3 - 0, pa7, pb5, and pc7 - 0 can be used as i/o or i/o with external interrupt sources. for external interrupt sources, pa3 - 0 interrupt are enabled or disabled by mask option and controlled by irqe ($0006). pa7 is enabled or disabled by irqe1 ($0006). pb5 is enabled or disabled by irqe ($0006). pc7 - 0 is enable or disable by register irqe2 ($0006). for more details on interrupt statements, please see interrupt section. 21. slow transition enable (sle) - $0009 (rpa) bit7 (see appendix d) pa6, pa7, pb1 and pb2 pin have slow transition signal output function (sle). if this function is enabled ($0009 bit7 = 1), the transition time of outputs is 250ns 20% with 50pf (pb), 500pf (pa) load at 2.0mhz. when sle ($0009 bit7) = 0, the slow transition output is disabled. example: pa6, pa7 & pb1, pb2 set as output and have slow transition function. lda #%11000000 sta dpa ;dpa $0002, set pa6, ;pa7 as output lda #%00000110 sta dpb ;dpb $0003, set pb1, ;pb2 as output lda #%1xxxxxxx ;x = user-define sta rpa ;and set sle as ?1? for ;enable slow ;transition. lda #ffh sta temp ;tem p = a register of ;$80h~ffh loop1: lda temp eor #c6h ;cross-change b6, b7 ;& b1, b2 sta temp sta pa ;pa6, pa7 output ;pulse. sta pb ;pb1, pb2 output ;pulse ldx #00h ;delay loop2: dex bne loop2 jmp loop1 ;repeat output of ; pa6, pa7, pb1. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 9 nov. 07, 2000 version: 1.5 no enable slow transition pa6 pb1 pa7 pb2 enable slow transition with capacitor no slow transition slow transition cpuclk pa6,pa7,pb1 pb2 falling edge delay phase 90 degree falling & rising edge slow transition 500pf 500pf 50pf pa6 pb1 pa7 50pf pb2 reset - see appendix e (reset block diagram) 1. external reset (reset pin) (see appendix e, h) the reset/pb4 pin can be selected to i/o or i/o with reset function by mask option. when reset is selected through mask option, the reset pin is the only external reset source with active-low polarity. this pin is connected to a schmitt trigger input gate & low active. note*: when using reset function, the dpb b4 must be set to input mode (b4 = 0), and rpb b4 set to pull-up resistor (b4 = 0) 2. power on reset (see appendix h) this reset is an internal reset. the power-on-reset will generate the reset signal that will reset the cpu until oscillator stabilized. to confirm the power on reset is generated properly, the system power should be held at a zero potential with respect to ground. improper initial setting of the power might cause the system can not work properly. the cpu will become active after 4096 clock cycles. 3. watch dog timer reset ($0007 bit0 wdt) (see appendix h, j) the watch-dog timer can be disabled or enabled through mask option. the internal reset of watch-dog is generated by a time-out of the watch-dog timer automatically when watch-dog is enabled. it is implemented on this device by using the output of the rti circuit and further dividing it by eight (rt1, rt0 timing times 8). this time-out generates reset if the wdt register is not cleared. an internal reset is generated and reset vector is fetched. preventing a wdt time-out reset is done by writing a ?1? to wdt ($0007 b0) within a specific time. the minimum wdt reset time is listed in (rt1, rt0) & wdt interrupt frequency table. addr register r/w 7 6 5 4 3 2 1 0 enable $0007 watch dog r cpd1(0) cpd0(0) cpif(0) (0) (0) wdt timer status w cprs1 cprs0 cpie cpiph cpe wdt(0) 1 = clr example: clear watch-dog timer mainloop: jsr clear_wdt .... ;long program will ;over watch-dog ;timer jsr clear_wdt ;so need call clear ;wdt subroutine ;again. .... ;some work. jmp mainloop clear_wdt: lda cpwd_stu ora #01h ;only set b0 = 1. sta cpwd ;wdt ($0007), clear ;$0007 b0 wdt ;register. rts 4. illegal address reset (iar) (see appendix h) the internal reset of iar is generated when an instruction op-code fetch occurs from an address that is not implemented in the ram ($0080-$00ff) nor rom ($0400-$17ff). the iar will generate the reset signal that will reset the cpu and other peripherals. 5. low voltage reset (lvr) (see appendix h) the internal lvr reset is generated when vdd falls below the specified lvr trigger voltage (herein, 2.2v) for at least one cpu clock cycle. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 10 nov. 07, 2000 version: 1.5 interrupt - see appendix a, c, f, i (interrupt diagram) 1. software interrupt (brk) the brk is an executable instruction interrupt since it is executed regardless of the state of the i-bit in the processor status register flag (inside cpu). when brk is occurred, it jumps to irq_routine. 2. external interrupt the external interrupt sources include irq/pb5 pin, pa3 - 0, pa7 and pc7 - 0. the pa3 - 0 can be mask option as i/o or i/o with an external interrupt function. the irq/pb5 pin provides an interrupt to the cpu by program control (see i/o port b section). pa7 and pc7 - 0 can also be programmed as an external interrupt (see i/o port a section and i/o port c section). the pa7 and irq/pb5 pin are designed with schmitt trigger input and low active, but pa3 - 0 and pc7 - 0 are high active. addr register r/w 7 6 5 4 3 2 1 0 enable $0006 irq control & r 0(0) 0(0) irqf2 irqe2 irqf(0) irqf1(0) irqe1 irqe irqs status w irqr1 irqr (0) (0) (0) (0) 1 = set 1). the b0 irqe is pa3 - 0 & irq pin interrupt enabling control. (1 as enable, 0 as disable). 2). the b1 irqe1 is pa7 interrupt enabling control. (1 as enable, 0 as disable). 3). the b2 irqf1 is pa7 irq flag. when b2 = 1, it indicates pa7 generates interrupt. when b2 = 0, no interrupt is generated. it is read-only. 4). the b3 irqf is pa3 - 0 & irq pin irq flag. when b3 = 1, it indicates pa3 - 0 & irq pin generate interrupt. when b3 = 0, no interrupt is generated. it is read-only. 5). the b4 irqe2 is pc7 - 0 interrupt control bit. (b4 = 1 as enable interrupt, b4 = 0 as disable). 6). the b5 irqf2 is pc7 - 0 irq flag. (b5 = 1 has interrupt generated. b5 = 0, no interrupt). it is read-only. 7). the b6 irqr is a write-only bit for clearing irqf flag. (1 as clear active, 0 as no clear). 8). the b7 irqr1 is a write-only bit for clearing irqf1 flag. (1 as clear active, 0 as no clear) 3. irq, pa3 - 0 interrupt (see appendix a, f, i) the irq/pb5 pin can be selected as i/o or i/o with irq function by program. when irq function is selected, the irq pin is the main external source of an interrupt with active-low polarity. this pin is connected to a schmitt trigger input. it is an open-drain mode and therefore an external pull-up resistor is required. when pb5 i/o function is selected, the pb5 pin is normal i/o with open-drain always. when irqe1 is disabled, the irqf will be cleared during creating interruption. however, if irqe1 is enabled, the irqf will not be cleared by interrupt. this interrupt source can be either " edge-trigger" or "level-trigger". it is selected by mask option. if mask option is set to 'edge-trigger' mode, the following conditions will generate irq interrupt: 1). falling edge on the irq pin. 2). rising edge on any of pa3 - 0 pin. (during pa3 - 0 mask option enabled.) if mask option is set to ?edge-level trigger? mode, the following conditions will generate irq interrupt: 1). falling edge and low level trigger on the irq pin. 2). rising edge and high level on any of pa3 - 0 pins. (pa3 - 0 mask option enabled.) when irq pin or pa3 - 0 pins generate an interrupt (cpu will set irqf ($0006 bit3) = 1), the irqe (if $0006 bit0 = 1,enabled) controls whether the interrupt request being sent to cpu. the irqr ($0006 bit6) is the irq pin and pa3 - 0 pin interrupt acknowledge. when irqr = 1, it clears the interrupt flag irqf ($0006 bit3 = 0). 4. pa7 interrupt (see appendix c, i) the pa7 interrupt input is falling-edge trigger. it is controlled by irqe1 ($0006 bit1). when pa7 interrupt occurred, the irqf1 ($0006 bit2) will be set. the irqr1 ($0006 bit7) is the pa7 pin interrupt acknowledge. when irqr1 = 1, it will clear the pa7 interrupt flag irqf1 ($0006 bit2 = 0). free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 11 nov. 07, 2000 version: 1.5 5. pc7 - 0 interrupt (see appendix a, i) the pc7 - 0 interrupt inputs are rising edge trigger. it is controlled by irqe2 ($0006 bit4). when pc7 - 0 interrupt occurred, the irqf2 ($0006 bit5) will be set. to clear irqf2, disable irqe2 first and then set irqe2 again. as stated above, irqf2 will be cleared to ?0?. example: use irq pin, pa3 - 0, pa7 and pc7 - 0 as interrupt. lda #00 sta dpa ;set pa, pc port to ;input sta dpc lda #%11010011 ;enable irq, pa3 - 0, ;pa7, pc 7 - 0 irq and ;clear int flag sta irqs ;irqs = $0006 .... ;other working irqvacter: lda irqs ;interrupt ;subroutine sta irqs_stu ;irq status register and #%00000100 ;check interrupt of ;pa7 bne pa7_irq lda irqs_stu and #%00100000 ;check interrupt pc7-0 bne pc_irq pa03_irq: lda irqs_stu and #%00001000 ;check interrupt of ;pa3 - 0 beq irq_end ;no pa3 - 0, pa7, ;pc7-0& external irq ;pin lda pa and #%00001111 ;check pa 3 - 0 create ;irq bne pa03_in irqp_in: .... ;irq pin interrupt ;works something. jmp pa03_end pa03_in: .... ;pa 3 - 0 interrupt ;work something. pa03_end: lda #%01010011 ;set pa3 - 0, pa7, ;pc7 - 0 clear ;pa3 - 0 flag. don?t jmp irq_end ;clear pa7, pc7 - 0 ;flag for next irq of ;pa7, pc7 - 0. pa7_irq: .... ;pa7 interrupt works ;something. lda #%10010011 ;set pa3 - 0, pa7, ;pc7-0& clear pa7 ;flag, don?t jmp irq_end ;clear pa3 - 0,pc flag ;for next irq of ;pa3 - 0,pc pc_irq: .... ;pc 7 - 0 interrupt ;work something. lda irqs_stu and #%11001111 ;clear pc 7 - 0 irq flag sta irqs ora #%00010011 ;set pa3 - 0, pa7, ;pc7-0& clear pc ;flag, don?t clear ;pa3 - 0, pa7 flag for ;next irq irq_end: sta irqs rti 6. timer interrupt (timer) (see appendix j, k) the timer interrupt is generated when timer1 or timer2 overflows or a real time interrupt has occurred. the timer interrupt flags (tof1, tof2, rtif), enable bits (tofe1, tofe2, rtie) and timer interrupt acknowledge bits (tofr1, tofr2, and rtifr) are designed for the timer interrupt. there are located in the timer control & status register 1 (tcs1) (address at $0004) and timer control & status register 2 (tcs2) (address at $000e). the i-bit in the processor status flag (inside cpu) must be cleared to ?0? for enabling interrupt (use cli instruction). for more details on settings of the timer control & status register (tcs), please see the multi-function timer section. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 12 nov. 07, 2000 version: 1.5 7. comparator interrupt (see appendix b) the comparator generates the comparator interrupt. it can compare external input (pa4 or pa5) (set cpwd $0007 b3 cpe & b5 cpie for enabling) voltage with internal reference voltage 1.2v or external reference voltage on pb0 (selected by cpwd $0007 b6 cprs0 and b7 cprs1). it is controlled by cpiph (cpwd $0007 b4) that whether the input voltage is higher (lower) than reference voltage. when $0007 b5 (cpie) is enabled (=1) for comparison, it needs to be disabled (set to ?0?) when sleep. without disable cpie, it may consume current while sleeping. addr register r/w 7 6 5 4 3 2 1 0 enable $0007 watch dog r cpd1(0) cpd0(0) cpif(0) (0) (0) (0) 1 = clr cpwd timer status w cprs1 cprs0 cpie cpiph cpe wdt /set 1). the wdt is a watch-dog timer clear register. see watch dog timer reset section. 2). the b3 cpe is a control bit to enable or disable comparator function. it is a write-only bit. 3). the b4 cpiph controls less or over than vref. it is a write-only bit. 4). the cpie is a comparator irq enabling bit (1: enable, 0: disable). it?s available in write mode. the cpif is irq flag for program check (1 indicates interrupt, 0 indicates no interrupt). it is available in read mode. 5). the cprs0 selects comparator 0(pa4) reference voltage vref, using internal default 1.2v or external reference from pb0 input (1 as choose pb0, 0 as choose 1.2v). it?s is available in write mode. the cpd0 is the flag for compare result (0 as happen, 1 as no happen). it is available in read mode. 6). the cprs1 selects comparator 1(pa5) reference voltage, using internal default 1.2v or external reference from pb0 input. (1 as choose pb0, 0 as chooses 1.2v). it is available in write mode. the cpd1 is the flag for compare result. (0 as happen, 1 as not happen). it is available in read mode. the comparator programming method can be accomplished as follows: 1). check cpif through irq routine, then check cpd0 and cpd1 to identify which one is generated. 2). use polling method. check cpd0 and cpd1 to identify that is generated occasionally. example: use irq routine to acknowledge comparator result lda #%10101001 ;enable comparator & ;irq, pa4 vref = 1.2v, sta cpwd ;pa5 vref = pb0, ;cpwd = $0007. .... cli irqvacter: lda cpwd sta cpwd_stu ;comparator status ;register. and #%00100000 ;only check cpif. beq irq_end ;pa4, pa5 is not ;bigger then vref. so ;no irq flag. lda cpwd_stu and #%01000000 ;check pa4 ;comparator 0. bne pa5_com ;no cpd0 happen. pa4_com: .... ;vinpa4 > 1.2v so ;working some thing. jmp irq_end pa5_com: lda cpwd_stu and #%10000000 ;check pa5 ;comparator 1. bne irq_end ;no cpd1 happen. .... ;vinpa5 > vrefpb0 so ;working some thing. irq_end: lda #%00000001 ;clear cpif and wdt. sta cpwd lda #%00101001 sta cpwd ;set comparator ;again. rti free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 13 nov. 07, 2000 version: 1.5 example: use polling method to acknowledge comparator result lda #%10011001 ;pa4 vref = 1.2v, pa5 ;vref = pb0, enable ;cpe sta cpwd ;don?t use irq, ;compare less then ;vref. .... ;some thing works. jsr cp_pgm .... ;some thing works. jsr cp_pgm .... ;some thing works. cp_pgm: lda cpwd sta cpwd_stu and #%01000000 bne pa5_com ;no cpd0 happen. pa4_com: .... ;vinpa4 < 1.2v so ;working some thing. jmp cp_end pa5_com: lda cpwd_stu and #%10000000 ;check pa5 ;comparator. bne cp_end ;no cpd1 happen. .... ;vinpa5 < vrefpb0 so ;working some thing. cp_end: lda #%00000001 ;clear cpif and wdt. sta cpwd lda #%00101001 sta cpwd ;set comparator ;again. rts multi-function timer two types of timers are supported in SPMC02A. description is as follows: the timer1 for this device is a 15-bit multi-function ripple up-counter. the feature functions include timer overflow, real time interrupt (rti), power on reset and watch-dog timer reset (wdt). when the timer counter register 1 (tcr1 $0005) overflows, the timer overflow flag (tof1) will be set. tof1 = 1 will generate an interrupt request to cpu in case of timer overflow enable being set (tofe1 = 1). whenever tofr1 is set to ?1?, the tof1 flag bit will be cleared. the real time interrupt flag (rtif) will be set when 1 of 4 selections (rt1, rt0) is active. rtif = 1 will generate an interrupt request to cpu if real time interrupt enable is set (rtie = 1). whenever rtifr = 1, it will clear the rtif flag bit. when a reset is occurred, rt1 and rt0 of tcs1 are set as ?1? and rest of the bits on tcs are set as ?0?. when the timer counter register 2 (tcr2 $000f) overflows, the timer overflow flag (tof2) will be set. and tof2 = 1 will produce an interrupt request to cpu when timer overflow enable is set (tofe2 = 1). whenever tofr2 is set to ?1?, the tof2 flag bit will be cleared. the timer2?s content can be loaded by program, and re-loaded the same content by itself when interrupt occurs. the timer 1 cannot be loaded and re-loaded any data; it is an auto-counter. 1. timer 1 - see appendix j (timer 1 block diagram) the timer1 input clock can be mask option to be divided by 4 or original timer1 input clock. therefore, frequency of timer1 is f cpu /2 10 or f cpu /2 8 . frequency of timer2 is f cpu /2 14 ~2 17 or f cpu /2 12 ~2 15 . the 15-stage timer contains two registers: timer counter register 1 & timer control/status register 1. timer counter register 1 (tcr1) - $0005 the timer counter register 1 is a read-only register that contains 8-bit content at the beginning of the timer chain. the content of each bit of the tcr1 is shown in the following table. the register is cleared by reset. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 14 nov. 07, 2000 version: 1.5 addr register r/w 7 6 5 4 3 2 1 0 enable $0005 timer counter r tmr7(0) tmr6(0) tmr5(0) tmr4(0) tmr3(0) tmr2(0) tmr1(0) tmr0(0) tcr1 register w timer counter register 1 (tcr1) timer control/status register 1 (tcs1)- $0004 the tcs1 contains the timer interrupt flag (tof1, rtif), the timer interrupt enable (tofe1, rtie), timer interrupt acknowledge (tofr1, rtifr) and the real timer interrupt rate selection bits (rt1, rt0). bit 2 and bit 3 are write-only bits that will be read as logical zeros. the following table shows the content of each bit in the tcs. rt1 and rt0 of tcs are set as ?1? and rest of the bits on tcs are set as ?0? by reset initially. addr register r/w 7 6 5 4 3 2 1 0 enable $0004 timer control r tof(0) rtif(0) tofe rtie 0(0) 0(0) rt1 rt0 tcs1 & status w (0) (0) tofr rtifr (1) (1) 1 = set timer control/status register 1 (tcs1) 2. tof1 - timer 1 overflow flag (the tof1 is a read-only flag bit.) 1 = set when the 8-bit ripple counter rolls over from $ff change to $00. a timer interrupt request will be generated if tofe1 is also set. 0 = reset by writing a logical one to the tof1 acknowledgment bit, tofr1. 3. rtif - real time interrupt flag (the rtif is a read-only flag bit.) 1 = set when the output of the chosen real time interrupt stage goes active. a timer interrupt request will be generated if rtie is also set. 0 = reset by writing a logical ?1? to the rtif acknowledgment bit, rtifr. 4. tofe1 - timer 1 overflow enable the tofe1 is an enable bit that allows generating timer interrupt upon overflow of the timer counter register 1. 1 = when set, the timer interrupt is generated when the tof1 flag bit is set. 0 = when cleared, there is no timer interrupt being generated for tof1 flag. 5. rtie - real time interrupt enable the rtie is an enable bit that allows generation of a timer interrupt by the rtif bit. 1 = when set, the timer interrupt is generated when the rtif flag bit is set. 0 = when cleared, there is no timer interrupt being generated even though rtif flag is set. 6. tofr1 - timer 1 overflow acknowledge the tofr1 is an acknowledge bit that resets tof1 flag. reading the tofr1 will always return a logical zero. 1 = clears the tof1 flag bit. 0 = does not clear the tof1 flag bit. 7. rtifr - real time interrupt acknowledge the rtifr is an acknowledge bit that resets the rtif flag. reading the rtifr will always return a logical zero. 1 = clears the rtif flag bit. 0 = does not clear the rtif flag bit. 8. rt1: rt0 - real time interrupt rate select the rt0 & rt1 control bits select one of four types to let the real time interrupt circuit run. the following table shows the available interrupt rates for two frequency values of timer 1 clock selected by mask option. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 15 nov. 07, 2000 version: 1.5 example: cpu clock f cpu = 1.0mhz (oscillation frequency = 2.0mhz) with two options for timer 1 clock rti rates min. wdt reset (=rti/8) rt1:rt0 divider option f cpu /4 option f cpu /1 divider option f cpu /4 option f cpu /1 00 2048 8.192ms 2.048ms 16384 65.536ms 16.384ms 01 4096 16.384ms 4.096ms 32768 131ms 32.768ms 10 8192 32.768ms 8.192ms 65536 262ms 66ms 11 16384 65.536ms 16.384ms 131072 524ms 131ms (rt1, rt0) & wdt interrupt frequency table at f cpu = 1.0mhz example: enable timer counter 1 & rti (rt1 = 1, rt0 = 0), use 2.0mhz rosc. lda #%00111110 ;tcs1 $0004 set ;tofe1, rtie, rt1, ;rt0 = 10, sta tcs1 ;& clear ;interrupt flag .... ;other ;instruction for ;initialized or ;work cli ;software enable ;interrupt irq_vacter: lda tcs1 ;interrupt ;subroutine. and #%10000000 ;check timer ;overflow ;interrupt flag. bne to1_irq rti_irq: lda tcs1 and #%01000000 ;check real time interrupt beq irq_end .... ;working for used ;rti lda #%00110110 ;enable rti, to ;again, only ;clear rtif jmp irq_end to1_irq: .... ;working for used ;timer1 overflow lda #%00111010 ;enable rti, to ;again, only ;clear tof irq_end: sta tcs1 rti 9. timer 2 - see appendix k (timer 2 block diagram) the timer2 clock source can select to f cpu or external clock input (pb6) by program. it also can be divided with the scale defined by ps2-0 (tcs2 $000f b7-5), and it has a re-loadable timer counter register, so timer 2 frequency is f cpu ~ f cpu /2 16 (f pb6 ~ f pb6 /2 16 ). the timer2 contain two registers: timer counter register 2 & timer control/status register 2. timer counter register 2 (tcr2) - $000f the timer counter register 2 is re-loadable register. it can initialize data and re-load it data by itself when occur interrupt. the value of each bit of the tcr2 is shown in following table. the register is cleared by reset. addr register r/w 7 6 5 4 3 2 1 0 enable $000f timer counter r tm2r7 tm2r6 tm2r5 tm2r4 tm2r3 tm2r2 tm2r1 tm2r0 tcr2 register 2 w (0) (0) (0) (0) (0) (0) (0) (0) timer counter register 2 (tcr2) free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 16 nov. 07, 2000 version: 1.5 timer control/status register 2 (tcs2)- $000e the tcs2 contains the timer interrupt flag (tof2), the timer interrupt enable (tofe2), the timer interrupt acknowledge (tofr2), clock source (cks) and pre-scale selector (ps2 - 0). bit 2 is write-only bit that will be read as logical zeros. bit 1 is read-only whose data is not being cared in the write mode. the following table shows the content of each bit in the tcs2, which is set to 0 by reset. addr register r/w 7 6 5 4 3 2 1 0 enable $000e timer control r ps2 ps1 ps0 cks (0) (0) tof2 (0) tcs2 & status 2 w (0) (0) (0) (0) tm2e tofr2 (0) tofe2 1 = set timer control/status register 2 (tcs2) 10. ps2 - 0 - pre-scale selector these 3 bits can be selected to eight types of pre-scale status. the 000 as 2 0 , 001 as 2 1 , .... 110 as 2 7 , 111 as 2 8 . 11. cks - timer 2 clock source selector the cks is a selected bit for timer 2 counter clock source. 1 = select external clock source input from pb6 0 = select internal clock source from f cpu . 12. tm2e - timer 2 counter clock enable flag the tm2e is a control bit for counter clock. tofe2 is ineffective when this bit is 0. tofe2 is able to control whether timer 2 interrupt is generated or not during this bit is set to 1. 1 = enable timer 2 counter clock input. 0 = disable timer 2 counter clock input. 13. tofr2 - timer 2 overflow acknowledge (the tofr2 is a write-only bit.) the tofr2 is an acknowledgment bit that resets tof2 flag. reading tofr2 will always return a logical zero. 1 = clears the tof2 flag bit. 0 = does not clear the tof2 flag bit. 14. tof2 - timer 2 overflow flag (the tof2 is a read-only flag bit.) 1 = set when the 8-bit ripple counter rolls over from $ff change to $00. a timer interrupt request will be generated if tofe2 is also set. 0 = reset by writing a logical one to the tof2 acknowledge bit, tofr2. 15. tofe2 - timer 2 overflow enable the tofe2 is an enable bit that allows generating timer interrupt upon overflow of the timer counter register 2. this bit is ineffective when tm2e is disable (0). 1 = when set, the timer interrupt is generated when the tof2 flag bit is set. 0 = when cleared, no timer interrupt is generated even though tof2 is set. example: enable timer 2 & pre-scale 2 4 & load data #30h and use internal clock lda #30h ;initial tcr2 data. sta tcr2 ;tcr2 = $000f. lda #%10001101 ;tcs2 = $000e, ;pre-scale 2 4 , sta tcs2 ;enable tm2e, tofe2, ;clear tofr2. .... ;other working. cli irq_vacter: lda tcs2 ;interrupt ;subroutine and #%00000010 ;check timer ;overflow interrupt ;flag. beq irq_end tm2_irq: .... ;working for used ;timer 2 overflow. ;the tcr2 will ;re-load #30h again. irq_end: lda #%10001101 ; re-set tcs2 again & ;clear tofr2. sta tcs2 rti free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 17 nov. 07, 2000 version: 1.5 16. pwm - see appendix l (pwm generator block diagram) the clock source of pwm generator is obtained from timer 2 circuit. the timer 2 counter value is generated by 3 duty cycles wave generator or 64 duty cycles wave generator which are selected by pwms ($0010 b7) and then sent to pwm pulse output pb7 by pwme $0010 b6 controlled. the duty cycle of wave generator can be divided from (1/64high, 63/64 low) to (63/64 high, 1/64 low) with step 1/64 by pwm5 - 0 selected. the content of each bit in the pwmc is shown in following table, which is set to 0 by reset. addr register r/w 7 6 5 4 3 2 1 0 enable $0010 pwm waveform r (0) (0) pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 pwmc control w pwms pwme (0) (0) (0) (0) (0) (0) 1 = set pwm waveform control register (pwmc) 17. pwms - 3 duty cycle or 64 duty cycle generator selector the pwms is selected as 3-duty cycles generator or as 64-duty cycles by programming. 1 = selecting 64-duty cycles wave generator. duty value is controlled through bits pwm5 - 0. it can output high wave from 1/64 duty to 63/64 duty. 0 = selecting 3-duty cycles wave generator. it is fixed output 1/3 high & 2/3 low duty cycle. 18. pwme - pwm wave output enable flag the pwme is responsible for controlling pwm wave output to pb7. 1 = enabling pb7 output pwm wave; it will close pb7 i/o function for use of pwm pulse output only. 0 = disabling pwm output. 19. pwm5 - 0 - 6 bits pwm wave duty cycle controller the pwm5 - 0 are selected for pwm wave duty cycle. the value of selection is shown as follows: t1 range is t2 range is 1 64 duty duty 63 64 ~ 1 64 63 64 ~ t 2 t 1 f tm2v 64 cycle 1 3 2 3 fixed 1:2 duty f tm2v pwm5~0 t 1 t 2 000000 000001 000010 000011 111110 111111 1 64 63 64 pwms = 0 pwms = 1 2 64 62 64 3 64 61 64 62 64 2 64 63 64 1 64 example: enable tm2 & pwm output. lda #30h ;initial tcr2 data. sta tcr2 ;tcr2 = $000f. lda #%10001100 ;tcs2 = $000e, pre-scale ;2 4 , enable tm2e, sta tcs2 ;clear tofr2 for pwm ;only. lda #%11000111 ;enable pb7 output, ;select 64 duty, sta pwmc ;& set 7/64 high, 56/64 ;low, pwmc = $0010 .... ;other working. *you can measure the waveform with 7/64 duty high, 56/64 duty low at pb7. wait / stop mode the wait mode function will set cpu clock disabled and timer counter enabled if wait $0008 bit0 = 1 be set. the tof, rti, or external interrupt will make cpu recovered normally from wait mode interrupt point next address. the stop mode function will set cpu and timer counter disabled if stop $0008 bit4 = 1. only the external interrupt will make cpu and timer counter being recovered normally from stop mode interrupt point next address. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 18 nov. 07, 2000 version: 1.5 addr register r/w 7 6 5 4 3 2 1 0 enable $0008 stop & wait r snw w stop(0) wait(0) 1 = set example: .... ; normal working. wait_set: lda #%00000001 ;stpwat $0008, set ;wait mode enable. sta stpwat ;enter the wait mode. nop ;* nop ; jmp mainpgmloop stop_set: lda #%00010000 ;set stop mode ;enable. sta stpwat ;enter the stop mode. nop ;* nop ; jmp mainpgmloop note*: to add two more nops to ensure proper wake up is preferred. pin description description mnemonic pin no. normal function external input port pull-up/down register source/sink vdd 28 i (power) vss 27 i (ground) xo/r 4 i (crystal in or resistor) xi 5 o (crystal out or ext. clock in) pa3 - 0 20 - 23 normal i/o ext. int (edge/level high) up, down (100k) -8/8ma pa4 12 normal i/o comparator 0 input up, down (100k) -8/8ma pa5 11 normal i/o comparator 1 input up, down (100k) -8/8ma pa6 10 i/o (open-drain o) slow transition output up (5k) -/8ma pa7 9 i/o (open-drain o) ext. int (edge low) / slow transition output up (5k) -/8ma pb0 13 normal i/o comparator reference input up, down (100k) -8/8ma pb1, pb2 29, 30 i/o (open-drain o) slow transition output up (100k) -/25ma pb3 3 normal i/o up, down (100k) -8/8ma reset/pb4 6 normal i/o ext. reset up (100k) -8/8ma irq/pb5 24 i/o (open-drain) ext. irq (edge/level low) (pull-up resistor on outside) -/8ma pb6 14 normal i/o external clock up, down (100k) -8/8ma pb7 19 normal i/o pwm waveform output up, down (100k) -8/8ma pc7 pc6 pc5 - 4 pc3 pc2 pc1 pc0 32 1 17 - 16 31 2 18 15 normal i/o external int (edge high) up, down (100k) -8/8ma pd3 - 2 pd1 - 0 8 - 7 26 - 25 normal i/o up (100k) -/8ma free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 19 nov. 07, 2000 version: 1.5 pin assignment xo/r xi pb4 pa7 pa6 pa4 pa5 pb0 pb1 vdd vss pb5 pa0 pa2 pa1 pa3 16 pin dip package 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 17 18 xo/r pb3 xi pb4 pa7 pa6 pa4 pa5 pb0 pb1 pb2 vdd vss pb5 pa0 pa2 pa1 pa3 18 pin dip package 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 20 19 17 18 xo/r pb3 xi pb4 pa7 pa6 pa4 pa5 pb0 pb6 pb1 pb2 vdd vss pb5 pa0 pa2 pa1 pa3 pb7 20 pin dip package 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 24 23 21 22 20 19 17 18 pc2 xo/r pb3 xi pb4 pa7 pa6 pa4 pa5 pb0 pb6 pc0 pc3 pb1 pb2 vdd vss pb5 pa0 pa2 pa1 pa3 pb7 pc1 24 pin dip package 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 28 27 25 26 24 23 21 22 20 19 17 18 pc6 pc2 xo/r pb3 xi pb4 pa7 pa6 pa4 pa5 pb0 pb6 pc4 pc0 pc7 pc3 pb1 pb2 vdd vss pb5 pa0 pa2 pa1 pa3 pb7 pc5 pc1 28 pin dip package 1 2 4 3 5 6 8 7 9 10 12 11 13 14 16 15 32 31 29 30 28 27 25 26 24 23 21 22 20 19 17 18 pc6 pc2 xo/r pb3 xi pb4 pd3 pd2 pa7 pa6 pa4 pa5 pb0 pb6 pc4 pc0 pc7 pc3 pb1 pb2 vdd vss pd0 pd1 pb5 pa0 pa2 pa1 pa3 pb7 pc5 pc1 32 pin dip package absolute maximum rating power supply voltage vdd = +2.4v to + 5.5v input voltage v in = - 0.3v to vdd+0.3v output voltage v out = 0v to vdd cpu clock from 200khz to 6.0mhz operating ambient temperature t opr = - 0 c to +70 c storage temperature t str = -20 c to +70 c note: stresses beyond those given in the absolute maximum ratings table may cause operational errors or damage to the device. for no rmal operational conditions see ac/dc electrical characteristics. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 20 nov. 07, 2000 version: 1.5 dc electrical characteristics (25 c, vdd = 5.0v) characteristic condition symbol min. typ. max. unit output high voltage pa5-0, pb7-6, pb4-3, pb0, pc7-0, pd3-0 i oh = -8ma v oh 2.4 - - v output low voltage pa7-0, pb7-3, pb0, pc7-0, pd3-0 i ol = 8ma v ol - - 0.4 v output low voltage pb1, pb2 i ol = 25ma v ol - - 0.5 v input high voltage pa5-0, pb7, pb6, pb3-0, pc7-0, pd3-0 vdd = 5.0v v ih 3.5 - - v input low voltage pa5-0, pb7-6, pb3-0, pc7-0, pd3-0 vdd = 5.0v v il - - 1.4 v positive-going input threshold voltage pa6, pa7, irq/pb4, reset/pb5 vdd = 5.0v v ih - 2.0 - v negative-going input threshold voltage pa6, pa7, irq/pb4, reset/pb5 vdd = 5.0v v il - 0.8 - v pull-up/down resistance pa5-0, pb7, pb6, pb3, pb0, pc7-0 v in = 5.0v /v in = 0v r pudwn /r pullup - 100 - k ? pull-up resistance pa6, pa7 pull-up always v in = 0v r pullup - 5.0 - k ? pull-up resistance pb1, pb2, pb4, pd3-0 v in = 0v r pullup - 100 - k ? i/o port hi-z leakage pa5 - 0, pb7 - 0, pc7 - 0, pd3 - 0 pull-down/up inactivated i iz - - 10 a power consumption i cc - tbd - ma stand by current i stb - 5.0 - a lvr trigger voltage v lvr - 2.2 - v free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 21 nov. 07, 2000 version: 1.5 the relationship between the r osc and the f osc 1. vdd = 3.0v , t a = 25 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 200 400 600 800 rosc ( kohms ) f cpu ( mhz ) 2. vdd = 5.0v , t a = 25 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 200 400 600 800 rosc ( kohms ) f cpu ( mhz ) 3. frequency vs. temperature 010203040506070 0.96 1.00 0.98 1.02 1.04 temperature ( ) f cpu /f cpu (25 ) frequency normalized to 25 rosc=91kohms v dd =4.5v v dd =3.0v 0.94 4. frequency vs. vdd 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 2345 v dd (volts) f cpu (mhz) rosc = 24 kohms rosc = 91 kohms free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 22 nov. 07, 2000 version: 1.5 appendix a: pa5 - 0, pb0, pb3, pb6, pb7, & pc7 - 0 i/o diagram 0 = in / 1 = out dpa ($0002) dpb ($0003) dpc ($000d) pa write ($0000) pb write ($0001) pc write ($000c) rpa ($0009) rpb ($000a) rpc ($000b) rst pa read ($0000) pb read ($0001) pc read ($000c) 0 = enable / 1 = disable pa5-0 & pb0,pb3,pb6,pb7, pc7-0 i/o diagram output -8ma drive & 8ma sink capability mask option (enable pull-up or enable pull-down when as input) pa0 ~ pa3 , pc0~pc7 only : to irq interrupt system p.s. : pb == port b data ($0001) dpb == port b direction control ($0003) rpb == port b pull-up / pull-down control ($000a) rst == chip internal reset signal data register bit pull-(up/down) register bit pwr 100k 100k 0 is short 1 is open 0 is short 1 is open 0 1 0 is open 1 is short 0 is open 1 is short data direction register bit i/o pin p.s. : pa == port a data ($0000) dpa == port a direction control ($0002) rpa == port a pull-up / pull-down control ($0009) rst == chip internal reset signal p.s. : pc == port c data ($000c) dpc == port c direction control ($000d) rpc == port c pull-up / pull-down control ($000b) rst == chip internal reset signal free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 23 nov. 07, 2000 version: 1.5 appendix b: comparator block diagram $0007 (cpwd) comparator & wdt r w w w w w r dff d ck clr q qn constant voltage source (1.2v) pb0 op + - 0 1 0 1 0 1 0 1 irqc en r pa4 pa5 (external v ref ) (external comparater0 ) (external comparater1 ) (to interrupt block) comparator block diagram 1.2v output op + - wdt x cpe x cpiph cpif/ cpie cpd1/ cprs1 cpd0/ cprs0 en en v in0 v in1 v ref0 v ref1 cprs0 cprs1 cpd1 cpd0 cprs v ref = 1.2v v ref = v pb0 0 1 mode cpiph cpd = 1 (v in > v ref) cpd = 1 (v in < v ref) 0 1 mode cpd0 cpd1 free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 24 nov. 07, 2000 version: 1.5 appendix c: pa6, pa7 i/o diagram rst pwr pa7-6 i/o diagram 8ma sink capability (open - drained type ) i/o pin ( vih = 2.0v , vil = 0.8v ) pa7 only : to irq interrupt system 5k (always enable) p.s. : pa == port a data ($0000) dpa== port a direction control ($0002) rpa == port a pull-up / pull-down control ($0009) rst == chip internal reset signal open-drain output 0 1 0 is open 1 is short 0 is open 1 is short data register bit pull-up register bit 0 = in / 1 = out data direction register bit rpa write ($0009) pa read ($0000) slow enable ($0009 rpa bit7 = 1) pa write ($0000) dpa write ($0002) free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 25 nov. 07, 2000 version: 1.5 appendix d: pb1, pb2 i/o diagram pb1, pb2 i/o diagram dpb write ($0003) pb write ($0001) rpb write ($000a) rst pb read ($0001) pwr 25ma sink capability (open - drained type ) slow enable ($0009 rpa bit7 = 1) i/o pin p.s. : pb == port b data ($0001) dpb == port b direction control ($0003) rpb == port b pull-up / pull-down control ($000a) rst == chip internal reset signal 100k open-drain output 0 1 no slow transtion slow transtion cpuclk pb1 pb2 slow change at raising & falling edge delay phase 90 degree data register bit 0 = enable / 1 = disable pull-up register bit 0 = in / 1 = out data direction register bit 0 is open 1 is short 0 is open 1 is short 0 is short 1 is open free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 26 nov. 07, 2000 version: 1.5 appendix e: reset & pb4 i/o diagram dpb write ($0003-b4) pb write ($0001-b4) rpb write ($000a-b4) rst pb read ($0001-b4) reset (pb4) output reset in or i/o pin -8ma drive & 8ma sink capability p.s. : pb == port b data ($0001) dpb == port b direction control ($0003) rpb == port b pull-up / pull-down control ($000a) rst == chip internal reset signal pwr to mreset (reset block diagram) mask option (reset input function enable or disable) 100k 0 1 0 is open 1 is short 0 is open 1 is short 0 is short 1 is open 0 = in / 1 = out data direction register bit 0 = enable / 1 = disable pull-up register bit data register bit free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 27 nov. 07, 2000 version: 1.5 appendix f: irq & pb5 i/o diagram dpb write ($0003-b5) pb write ($0001-b5) rst pb read ($0001-b5) irq (pb5) open-drain output irq in or i/o pin 8ma sink capab ility to mirq (interrupt source diagram) p.s. : pb == port b data ($0001) dpb == port b direction control ($0003) rpb == port b pull-up / pull-down control ($000a) rst == chip internal reset signal 0 1 0 is open 1 is short 0 is open 1 is short data register bit 0 = in / 1 = out data direction register bit (open - drained type) free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 28 nov. 07, 2000 version: 1.5 appendix g: pd3 - 0 i/o diagram 0 = in / 1 = out dpd write ($0011) pd write ($0012) rpd write ($0013) rst 0 = enable / 1 = disable pd3 - 0 i/o diagram output data direction register bit i/o pin -8ma drive & 8ma sink capability p.s. : pd == port d data ($0012) dpd == port d direction control ($0011) rpd == port d pull-up / pull-down control ($0013) rst == chip internal reset signal data register bit pull-up register bit pwr 100k pd read ($0012) 0 is open 1 is short 0 is open 1 is short 0 is short 1 is open 0 1 free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 29 nov. 07, 2000 version: 1.5 appendix h: reset block diagram reset block diagram clock address data vdd vdd mreset watchdog timer reset (wdt) illegal address (iladr) power-on reset (por) low voltage reset (lvr) address rst (to cpu & peripherals) mask option (wdt input function enable or disable) mask option (lvr function enable or disable) free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 30 nov. 07, 2000 version: 1.5 appendix i: interrupt source diagram interrupt source diagram pa0 pa1 pa2 pa3 ( mask option ) (port ext. int) rst irqr irqe1b ( irq fetch vector ) ( mask option) (irq level) irqe irqe1 pa7 rst irqr1 pwr irqf1 irqex (to irq in cpu) irqf pwr d ck rn q qn dfri (edge / edge - level) d ck rn q qn dfri irqs ($0006 - b3) mirq d c b a qn irqs ($0006 - b2) irqs ($0006 - b6) irqs ($0006 - b0) irqs ($0006 - b1) (internal reset signal) irqs ($0006 - b7) (internal reset signal) (~irqe1) irqc (from comparator block) pc0 pc4 pc3 pc2 pc1 pc5 pc7 pc6 d ck rn q qn dfri irqe2 irqs ($0006 - b4) irqv2 (from timer 2 block) irqi (from timer 1 block) (from irq/pb5) irqf2 irqs ($0006 - b4) 0 is open 1 is short 0 is open 1 is short 0 is open 1 is short free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 31 nov. 07, 2000 version: 1.5 appendix j: timer 1 block diagram tm1r7 tm1r2 tm1r3 tm1r4 tm1r5 tm1r6 tm1r1 tm1r0 $0005 (tcr) timer counter rigister tof rtifr tofr rtie tofe rtif rt1 rt0 $0004 (tcs) timer control & status rigister overflow detect circuit rti select circuit counter to power on reset (por) irqt timer 1 block diagram d ck clr q qn dff pwr d ck clr q qn dff pwr 8 watch dog timer to reset block watch dog clear f cpu fosc external timer clock (rosc / crystal) 4 internal timer clock 2 f tm1 2 9 f cpu mask option (f cpu divided dy 4 or no divided) 1 = clear (to interrupt block) irqv1 f tm1 f tm1 2 8 f tm1 2 12 f tm1 2 11 f tm1 2 10 f tm1 2 14 f tm1 2 13 f cpu 2 2 irqi 0 is open 1 is short 0 is open 1 is short free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 32 nov. 07, 2000 version: 1.5 appendix k: timer 2 block diagram f cpu ext. clk (pb6) pre-scale select f tm2 f tm2 overflow detect circuit auto re-load $000f (tcr2) timer counter register 2 pre-scale counter 8 to 1 selecter 0 4321 765 tm2r0 tm2r1 tm2r3 tm2r2 tm2r4 tm2r5 tm2r7 tm2r6 r w w w w w w w w r r rr rr ps2 cks ps0 ps1 tm2e tofe2 tof2 tofr2 pwr dff d ck clr q qn irqv2 (to interrupt source block) $000e (tcs2) timer 2 control & status (to pwm generator block) tm2v timer 2 block diagram ckin f tin f tm2 2 2 f tm2 2 3 f tm2 2 6 f tm2 2 4 f tm2 2 5 f tm2 2 7 f tm2 2 8 f tm2 2 1 f tin 2 0 f tin 2 2 f tin 2 3 f tin 2 4 f tin 2 5 f tin 2 6 f tin 2 7 f tin 2 1 0 1 free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 33 nov. 07, 2000 version: 1.5 appendix l: pwm generator block diagram pwm wave counter generator 64 duty cycle pwm pulse output (pb7) pwm wave generator 3 duty cycle tm2v (from timer 2 block) pwm generator block 1 3 2 3 fixed 1:2 duty t 1 range is t 2 range is 1 64 duty duty 63 64 ~ 1 64 63 64 ~ pwm5~0 t 1 t 2 00000 00001 00010 00011 00100 00101 11110 11111 1 64 63 64 2 64 62 64 3 64 61 64 4 64 60 64 5 64 59 64 62 64 2 64 1 64 63 64 t 2 t 1 f tm2v 64 cycle 0 1 f tm2v $0010 pwm control register pwm0 pwm3 pwm2 pwm1 pwm4 pwm5 pwme pwms pwme = 1 : dsiable pb7 i/o function for pb7 used to pwm output free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 34 nov. 07, 2000 version: 1.5 appendix m: bonding diagram x y (0,0) 3 pb3 30 pb2 29 pb1 9 pa7 10 pa6 11 pa5 23 pa0 22 pa1 13 pb0 18 pc1 19 pb7 1 pc6 32 pc7 31 pc3 2 pc2 28 vdd 21 pa2 25 pd0 26 pd1 14 pb6 15 pc0 16 pc4 17 pc5 12 pa4 7 pd2 8 pd3 4 xo/r 24 irq/pb5 27 vss reset/pb4 6 5 xi 20 pa3 chip size: 1900 m x 1970 m the ic substrate should be connected to vss note: 0.1 f capacitor between vdd and vss should be placed to ic as close as passible. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 35 nov. 07, 2000 version: 1.5 bonding coordinate pad no pad name x y 1 pc6 54 786 2 pc2 -107 786 3 pb3 -277 786 4 xo/r -439 767 5 xi -605 767 6 reset / pb4 -749 532 7 pd2 -749 367 8 pd3 -749 216 9 pa7 -749 47 10 pa6 -749 -121 11 pa5 -749 -290 12 pa4 -749 -451 13 pb0 -741 -784 14 pb6 -579 -784 15 pc0 -410 -784 16 pc4 -249 -784 17 pc5 -80 -784 18 pc1 82 -784 19 pb7 251 -784 20 pa3 749 -778 21 pa2 749 -609 22 pa1 749 -447 23 pa0 749 -278 24 irq / pb5 722 -117 25 pd0 749 48 26 pd1 749 199 27 vss 749 358 28 vdd 749 508 29 pb1 715 786 30 pb2 554 786 31 pc3 385 786 32 pc7 223 786 free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 36 nov. 07, 2000 version: 1.5 disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by sunplus technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. sunplus makes no warranty, express, statutory implied or by description regarding the information in this publicati on or regarding the freedom of the described chip(s) from patent infringement. further, sunplus makes no warranty of merchantability or fitness for any purpose. sunplus reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information i n this publication are current before placing orders. products described herein are intended for use in normal commercial application s. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equip ment, are specifically not recommended without additional processing by sunplus for such applications. please note that application circ uits illustrated in this document are for reference purposes only. free datasheet http://www.0pdf.com
SPMC02A ? sunplus technology co., ltd. page 37 nov. 07, 2000 version: 1.5 revision history date revision # description page nov. 04, 1997 0.1 original sep. 17, 1997 0.2 1. modify ? block diagram ? 2. modify grammar jan. 09, 1998 0.3 1. add operation voltage range: 2.4v - 6.0v in ? features ? and ? dc electrical characteristics? 2. chang font: ?arial" 3. add " emulation board " and " piggy back board " user guide mar. 02, 1998 1.0 delete ? preliminary ? mar. 21, 1998 1.1 1. change voltage range value: 2.4v - 6.0v to 2.4v - 5.5v 2. change footer font: ?times new roman? 1, 28, 29 jun. 04, 1998 1.2 1. add ? frequency vs. vdd, temperature ? 2. revise the pin naming in ? block diagram ?, ? pin assigment ?, ? bonding diagram ?, ? bonding corrdinate ?: osc2 -> xo, osc1 -> xi dec. 13, 1999 1.3 1. add pin no. in ? pin assignment ? 2. add ? disclaimer ? 3. renew to a new document format feb. 22, 2000 1.4 1. modify: $1800~$ffff -> $1800~$1fff in the ? block diagram ? 2. modify: table port a, b, c and d 6 - 9 nov. 07, 2000 1.5 1. wording improvement 2. to revise the cpu low bound clock range from 1khz to 200khz. 3. to correct the i/o block diagrams on appendix d: pb1 i/o diagram and appendix g: pb5 & irq i/o diagram. 4. to remove appendix e: i-v curve of pb1, appendix k: the emulation board and the jumper setting, and appendix l: piggyback board. 5. add ?note: the 0.1uf capacitor between vdd and vss?? 6. add ? revision history ? 7. renew to a new document format 34 37 free datasheet http://www.0pdf.com

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